What we do
Computing chips at the core, with the test and packaging that make them deliverable.
Chip research and development, IC application solutions and product sales, supported by a packaging and testing industry we are incubating in parallel.
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Three lines of business
01 Wholly owned
Computing chip design
Chip research and development, IC application solutions and product sales. The first generation covers automotive ADAS, central computing platforms and robot brain fusion; later generations move towards end-side central computing and cloud-side inference.
02 Joint venture
Automotive chip testing
An automotive test line planned to launch as our chips reach mass deployment in vehicles, run by a team with hands-on experience taking multiple chips through automotive-grade certification.
03 Joint venture
Advanced packaging
Incubated alongside chip design so that packaging and test grow as a supporting industry rather than a supplier relationship, part of building comprehensive in-house design and manufacturing capability.
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The integrated platform
Hardware and software are developed together, in-house, so performance is tuned across both rather than inherited from licensed IP.
Hardware
“Depth” NPU subsystem
A ring-bus computing architecture keeping compute, memory and host processor close together, so utilisation holds up on real workloads rather than only on benchmark kernels.
Software
“Ladder” compiler
An integrated RISC-V and NPU compiler: graph optimisation, operator fusion and instruction scheduling, the last mile that lets existing models run on our silicon without teams changing how they work.
Discipline
Automotive-grade flow
The full development flow runs to ISO 9001, and automotive products are developed to conform to ISO 26262. The bar that earns a place in a vehicle.
The “Ladder” software stack, layer by layer
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Layer 05
Your models
Application
The mainstream models developers already build on. Nothing here has to change to reach our silicon.
- Large language models
- Mainstream frameworks
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Layer 04
The last mile
Eco framework
Lets developers migrate models to our chips without changing mainstream development habits, and schedules work and resources across them.
- Data parallel
- Tensor parallel
- Pipeline parallel
- Sequence parallel
- Expert parallel
- Task scheduling
- KV cache management
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Layer 03
The performance core
“Ladder” core tools
The AI compiler and execution engine. Converts trained models into efficient execution plans tailored to the chip.
- Computation graph
- Compiler IR
- Semantic validation
- Graph partition
- Operator fusion
- Quantisation
- Layout transformation
- Loop transformation
- Tensor tiling
- Memory coalescing
- Instruction mapping
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Layer 02
The foundation
Infrastructure
Chip drivers, low-level libraries and runtime: the operating system of the chip, turning hardware into something the layers above can use.
- Compute libraries
- Communication libraries
- Custom operators
- Task scheduling
- Task pre-emption
- Error handling
- Memory management
- Device management
- Profiling
- FP32 / FP16 / BF16 / INT8 / INT4
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Layer 01
The silicon
“Depth” hardware
Self-developed NPU IP: tile clusters on a mesh NoC, threaded by a ring bus and fed by a RISC-V scheduler.
- Compute core
- Memory hierarchy
- Sync
- ISA
- NoC
Contact
Driving the future of intelligence.
Partners, investors and engineers: we would like to hear from you.