Hawk
SoC Architecture
20+ years in IC. Deputy Chief Engineer, Technical Director, CTO & Deputy GM of an automotive BU. Core contributor to HiSilicon Kirin AI IP.
About
A Malaysian chip company, rooted in automotive compute and reaching globally.
We focus on computing chips as our core business, while incubating the supporting industries of automotive chip testing and advanced packaging. Our goal is to become a world-class semiconductor group.
01 / 03
Company
Building a world-leading computing-chip cluster, from Malaysia outward.
Incorporated in April 2026 with RM 10,000,000 in registered capital, NoorTech is rooted in automotive compute and reaching globally, with R&D centres being established in China, North America, Europe and Japan, and joint ventures forming in packaging and test.
- Incorporated
- 2026
- Registered capital
- RM 10,000,000
- Headquarters
- Malaysia
- R&D centres, in registration
- Four regions
02 / 03
Vision and plan
With surging computing power, AI breathes life into machines.
Automotive intelligence and electrification, the growth of AI and the low-altitude economy are all asking for more compute. Over three to six years in high-compute SoCs we plan three leaps: catch up, surpass, lead, and set a benchmark for the industry.
Generation 1
Own the core
Self-developed NPU core IP, full SoC architecture and system verification, covering automotive ADAS, central computing platforms and robot brain fusion.
Generation 2
Everywhere at the edge
Builds on the first generation to lower cost and raise efficiency, moving towards ubiquitous end-side central computing in industrial and consumer products.
Generation 3
Into the cloud
Cloud-side inference on an advanced process with a more general-purpose NPU, building proprietary computing hardware on the first-generation platform.
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2026
Company founded, chip R&D started
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2028
First chip taped out
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2029
Chips mass-deployed in vehicles; automotive test line launched
03 / 03
Leadership
A top-tier NPU IP team, complemented by a high-compute SoC team.
Jason
NPU Architecture
Former AI chief expert at Huawei Smart Engineering. Lead architect on a first-generation cloud LLM inference chip. Former NPU architect at Qualcomm and NIO.
Oliver
NPU Compiler
PhD in compilation, Chinese Academy of Sciences. Led NPU architecture for a high-compute ADAS chip at sparse INT8 above 1000T.
Steven
SoC Design
15 years and 10+ mass-production chip programmes. Most recently responsible for cloud-side high-compute SoC architecture and design.
James
Software Solutions
20 years in chip system software across multimedia and AI, spanning edge-side and cloud-side high-compute inference.
Zora
Hardware Solutions
16 years in post-silicon test and hardware architecture. Automotive-grade certification across multiple vehicle-grade chips.
Contact
Driving the future of intelligence.
Partners, investors and engineers: we would like to hear from you.